Morgan Stanley Analysis: AI Chip Surge, Can Power Keep Up? Implied Demand of About 38GW by 2027

TL;DR
· Morgan Stanley estimates that with approximately 19 million GPUs/ASICs and an average TDP of 2kW per chip, the implied power demand for chips in 2027 will be about 38GW, with NVIDIA accounting for about 16GW.
· The 38GW is not the total electricity consumption of data centers or the already established power capacity, but rather a stress test to evaluate whether the infrastructure can handle the pressure of chip shipments.
· The report estimates that the demand for AI HBM in 2027 will be approximately 48.6 billion Gb, and the demand for CoWoS will be around 2.66 to 2.69 million units, although the Rubin Ultra layered memory solution has not yet been finalized.
· Google’s TPU shipments are expected to rise from 3.7 million units in 2026 to 7.35 million units in 2027, driving orders in the testing supply chain.

Morgan Stanley's latest Asian supply chain check translates AI expansion into a more intuitive power figure: estimating that with about 19 million implied GPUs and ASICs for CoWoS in 2027, and an average TDP of 2kW per chip, the corresponding power capacity for this batch of chips is approximately 38GW.

Among them, NVIDIA accounts for about 16GW, Google about 9GW, AMD about 7GW, AWS about 2GW, and Microsoft, Meta, and other manufacturers each about 1GW.

It is important to emphasize that the 38GW is not the total electricity consumption of global AI data centers at that time, nor is it the already confirmed power capacity. It does not fully account for the electricity used by CPUs, networking, storage, cooling, and other supporting facilities, but is closer to a stress test derived from chip shipment volumes: if AI accelerators are ramped up according to the supply chain model in 2027, can the power infrastructure keep pace with these chips?

This means that the constraints on AI computing power expansion are extending from "whether GPUs can be produced" to whether HBM, CoWoS, testing, rack delivery, and power access can all be in place simultaneously.

38GW Stress Test Pushes AI Bottleneck to Power

Morgan Stanley's calculation is based on two core assumptions: that the number of GPUs and ASIC chips corresponding to CoWoS in 2027 will be about 19 million, with an average TDP of 2kW per chip, leading to an implied power demand of about 38GW.

The 2kW is an average assumption used to estimate the total, and does not mean that all GPUs and ASICs have the same power consumption. The 38GW also does not equal the actual operational load of data centers, as chips will not always run at full load, and the CPUs, networking, storage, and cooling systems in servers will incur additional electricity usage.

However, this figure still holds reference value. Over the past two years, discussions in the AI supply chain have mainly focused on GPU production, HBM supply, and CoWoS capacity. As chip shipments continue to rise, grid access, substation construction, data center site selection, and long-term power purchase arrangements may directly affect whether chips can be converted into actual usable computing power.

Chip delivery is just the first step. Once GPUs or ASICs enter data centers, they also require servers, racks, networking, cooling, power, and operational systems to be in place. If infrastructure construction lags behind chip shipments, the market may experience a mismatch where "chips arrive, but the data center and power are not ready."

The implied power demand for GPU/ASIC chips in 2027 is about 38GW, with NVIDIA at 16GW, Google at 9GW, and AMD at 7GW.

For NVIDIA, the implied demand of 16GW also explains why the company continues to increase GPU density per rack. The report states that NVIDIA has long hoped to connect more GPUs through a scale-up architecture to enhance rack-level computing capability and performance.

However, the first-generation Rubin Ultra rack's Kyber solution still faces PCB and cooling challenges, and may continue to use the Oberon NVL72 design, expanding to NVL576 scale through CPO or NPO interconnects. Increasing rack density will not eliminate power demand; rather, it will concentrate the supply, cooling, and interconnect pressures on higher-spec data center designs.

HBM and CoWoS Expand in Sync, Rubin Ultra Specifications Still to be Determined

Beyond power, HBM and advanced packaging remain the main constraints for AI chip expansion around 2027.

According to Morgan Stanley's supply chain model, the HBM demand corresponding to AI chips in 2027 is estimated to be approximately 48.618 billion Gb. Exhibit 3 lists the CoWoS configuration quantity at about 2.664 million wafers, while Exhibit 5 gives the global CoWoS demand at about 2.694 million wafers, with slight differences due to varying statistical scopes.

The report also estimates that the market size for wafer revenue corresponding to AI computing chips will reach at least $58.8 billion by 2027. NVIDIA remains the largest demand side for CoWoS, expected to account for about 1.222 million wafers; AMD and Broadcom are expected to account for about 530,000 wafers and 484,000 wafers, respectively.

The AI HBM demand in 2027 is about 48.6 billion Gb, along with the CoWoS configurations and HBM demand for different GPUs and ASICs.

An important variable still exists in the demand forecast: the HBM configuration for Rubin Ultra has not yet been finalized.

Supply chain checks indicate that Rubin Ultra may adopt a layered specification, with the high-end version using HBM4e 8Hi, while the low-end version may use HBM4 12Hi or 8Hi. Morgan Stanley expects NVIDIA to make a final decision before the end of the third quarter of 2026.

This adjustment mainly reflects three pressures: HBM capacity shortages, rising memory costs, and the differing demands for capacity and bandwidth across various AI workloads. The report suggests that reducing HBM configuration may have a greater impact on decoding workloads than pre-filling, especially in large context models.

It is important to note that Exhibit 3 still calculates the HBM4e 12Hi configuration for Rubin Ultra, with a total capacity of 384GB per chip. Therefore, the 48.6 billion Gb HBM demand does not fully reflect the potential for a layered down-specification scheme. If the final configuration is lowered, the HBM usage per chip may decrease, but lower memory costs may also drive an increase in chip shipments, partially offsetting the impact of the decrease in per-chip usage.

Micron's public information indicates that its HBM4 has entered mass shipment stages, with HBM4E expected to go into production in 2027. The supply side is pushing new products, but what configuration Rubin Ultra ultimately adopts will still depend on NVIDIA's comprehensive assessment of performance, cost, and supply assurance.

The shipment rhythm of the Rubin series remains aggressive. The report estimates that shipments of Rubin and Rubin Ultra combined will approach 7 million units by 2027, with Rubin accounting for about 5.92 million units and Rubin Ultra about 1.04 million units; shipments of Rubin NVL72 racks may reach about 90,000 units.

Rubin is expected to ramp up starting in the third quarter of 2026, with rack shipments commencing in the fourth quarter. The report also believes that the previous market concerns about Blackwell "inventory" are more about supply chain buffer inventory, which is expected to be fully consumed by 2026.

Predictions for Rubin and Rubin Ultra chip shipments and Rubin NVL72 rack shipments.

This means that from the second half of 2026 to 2027, NVIDIA's supply chain needs to simultaneously complete the digestion of Blackwell inventory, ramp up Rubin, switch HBM specifications, and deliver racks. Any slowdown in one link may affect the final deliverable computing power scale.

Google TPU Increases to 7.35 Million Units, Orders Flowing to Testing Chain

Aside from NVIDIA, Google TPU is another clear growth line in the report.

According to Morgan Stanley's forecast, Google TPU shipments are expected to increase from 3.7 million units in 2026 to 7.35 million units in 2027. Among them, the v8i, involving Broadcom, is expected to ship 4 million units, the v8t, involving MediaTek, is expected to ship 3 million units, the v9 is expected to be about 150,000 units, and the remaining approximately 200,000 units will come from v7.

Predictions for Google TPU shipments across generations and their potential contribution to KYEC revenue.

The ramp-up of TPUs will transmit orders to chip design, wafer manufacturing, advanced packaging, and testing stages. The report estimates that TPU-related business may account for 7% to 8% of KYEC's revenue in 2026, with a slightly higher proportion of over 10% in 2027, including final testing and some wafer probing revenue.

If all of Google’s CPU, TPU, final testing, and some wafer probing businesses are included, the related demand from Google is expected to account for 10% to 15% of KYEC's revenue in 2027, up from 8% to 10% in 2026.

Testing demand is also becoming more complex. The report states that the 3nm TPU involving MediaTek is expected to adopt Burn-in testing to enhance the performance stability and reliability of AI chips; Google’s CPU project also requires Burn-in and system-level testing.

More complex testing processes and longer testing cycles will increase orders for testing factories, but whether testing capacity will become a bottleneck still depends on the joint changes in single-chip testing time and overall shipment volume. The report also notes that some reductions in testing time may alleviate recent capacity pressures, so testing demand growth cannot simply be equated with inevitable capacity shortages.

38GW is Not the Endpoint of Demand, But a Test of Delivery Capability

The most noteworthy aspect of this supply chain check is not just the provision of more AI chip shipment figures, but the placement of the main expansion constraints for 2027 within the same model: NVIDIA continues to increase GPU density, Google TPU ramps up quickly, HBM and CoWoS demand rises in sync, and the implied power demand for chips is pushed up to 38GW.

These figures still rely on multiple premises. The layered HBM scheme for Rubin Ultra has not yet been finalized, and the impact of reducing memory configurations on long-context decoding performance still needs verification; CoWoS and HBM capacity need to expand as planned; and server, rack, power, and cooling construction must keep pace with chip deliveries.

Interconnect schemes may also bring differences. The report states that due to local foundry process limitations, the SerDes speed of Chinese AI GPU manufacturers may still be stuck at 100Gb/s per channel, so their supernode architecture is adopting more NPO interconnects, while NVIDIA has long prioritized CPO. Different routes will affect supernode design, deployment costs, and system efficiency.

Therefore, 38GW is not an accurate prediction of actual electricity consumption in 2027, but rather a stress test derived from the chip shipment side. It shows that the demand for AI chips remains strong and reminds the market that what may determine whether AI computing power can be realized may no longer just be GPU production, but whether HBM, CoWoS, testing, racks, and power can all be in place at the same time.